MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 24

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

SELF REFRESH
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the
rest of the system is powered down. When in the self refresh mode, the DDR SDRAM
retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically dis-
abled upon entering SELF REFRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a READ command can be issued).
Input signals except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also
required for full duration of the SELF REFRESH cycle.
The procedure for exiting self refresh requires a sequence of commands. First, CK and
CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM
must have NOP commands issued for
tion of any internal refresh in progress. A simple algorithm for meeting both refresh and
DLL requirements is to apply NOPs for
additional clock cycles before applying any other command.
24
t
XSNR because time is required for the comple-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
XSNR time, then a DLL Reset and NOPs for 200
128Mb: x4, x8, x16 DDR SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands