MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 70

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
b. Reach at least the target AC level.
c.
a.
After the AC target level is reached, continue to maintain at least the target DC level, V
V
Sustain a constant slew rate from the current AC level through to the target AC level, V
V
IH
IH
(DC).
(AC).
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
16. Inputs are not recognized as valid until V
17. The output timing reference level, as measured at the timing reference point indi-
18. Transitions occur in the same access time windows as data valid transitions. These
19. The intent of the Don’t Care state after completion of the postamble is the DQS-driven
20. This is not a device limit. The device will operate with a negative value, but system
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
22.
23. The refresh period is 64ms. This equates to an average refresh rate of 15.625µs. How-
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
25.
26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7;
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
28. To maintain a valid level, the transitioning edge of the input must:
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
refresh mode, V
period before V
cated in Note 3, is V
parameters are not referenced to a specific voltage level, but specify when the device
output is no longer driving (
signal should either be high, low, or high-Z and that any signal transition within the
input switching region must follow valid input requirements. That is, if DQS transi-
tions high (above V
t
performance could be degraded due to bus turnaround.
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on
MIN (
meets the minimum absolute value for the respective parameter.
I
lute value for
ever, an AUTO REFRESH command must be asserted at least once every 140.6µs;
burst refreshing or posting by the DRAM controller greater than eight refresh cycles is
not allowed.
maximum amount for any given device.
The data valid window is derived by achieving other specifications -
t
portion to the clock duty cycle and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle variation of 45/55, because function-
ality is uncertain when operating beyond a 45/55 ratio. The data valid window
derating curves are provided in Figure 35 on page 71 for duty cycles ranging
between 50/50 and 45/55.
x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15.
during REFRESH command period (
standby).
DQSH(MIN).
DQSQ, and
DD
REF
measurements is the largest multiple of
.
t
RC or
t
QH (
t
t
RAS.
RFC) for I
REF
REF
t
stabilizes, CKE 0.3 x V
IH
QH =
TT
must be powered within specified range. Exception: during the
DC(MIN) then it must not transition low (below V
.
t
HP -
DD
70
t
HZ) or begins driving (
measurements is the smallest multiple of
t
QHS). The data valid window derates in direct pro-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
REF
DD
128Mb: x4, x8, x16 DDR SDRAM
stabilizes. Once initialized, including self
Q is recognized as LOW.
t
CK that meets the maximum abso-
t
LZ).
t
DQSS.
©2000 Micron Technology, Inc. All rights reserved.
t
RAS (MAX) for
IH
t
HP (
DC) prior to
IL
IL
t
CK that
(DC) or
Notes
(AC)
t
CK/2),
or