MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 85
![IC DDR SDRAM 128MBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V32M4TG-6T:D TR
Manufacturer Part Number
MT46V32M4TG-6T:D TR
Description
IC DDR SDRAM 128MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V32M4TG-6TD_TR.pdf
(93 pages)
Specifications of MT46V32M4TG-6T:D TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (32Mx4)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1024-2
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Figure 47:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
COMMAND
BA0, BA1
A0-A9,
DQS
A11
A10
DM
DQ
CK#
CKE
CK
5
5
5
1
1
1
1
Auto Refresh Mode
t
t
IS
NOP 2
IS
T0
t
IH
t
IH
Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank
ALL BANKS
ONE BANK
t
Bank(s) 4
IS
PRE
T1
2. NOP commands are shown for ease of illustration; other valid commands may be possible
3. NOP or COMMAND INHIBIT are the only commands allowed until after
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-
t
IH
Address.
at these times. CKE must be active during clock positive transitions.
must be active during clock positive transitions.
active (i.e., must precharge all active banks).
to-back AUTO REFRESH commands.
CK
VALID
NOP 2
T2
t
CH
t RP
t
CL
NOP 2
T3
85
T4
AR
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t RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP 2, 3
Ta0
128Mb: x4, x8, x16 DDR SDRAM
Ta1
AR 6
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VALID
NOP 2, 3
Tb0
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t RFC 5
NOP 2
Tb1
t
RFC time, CKE
DON’T CARE
Tb2
ACT
RA
RA
BA
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