MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 25

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Operations
Bank/Row Activation
Figure 10:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
Activating a Specific Row in a Specific Bank
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM,
a row in that bank must be “opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated, as shown in Figure 10.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.7 clocks rounded to 3. This is reflected in Figure 11, which covers any case
where 2 <
procedure is used to convert other specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time inter-
val between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
BA0, BA1
RRD.
A0-A11
RAS#
CAS#
WE#
CKE
CK#
CS#
CK
t
HIGH
RA = Row Address
BA = Bank Address
RCD (MIN)/
BA
RA
t
CK ≤ 3. (Figure 11 also shows the same case for
t
RCD specification of 20ns with a 133 MHz clock (7.5ns period)
25
t
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 DDR SDRAM
t
RCD (MIN) should be divided by
©2000 Micron Technology, Inc. All rights reserved.
t
RCD; the same
Operations
t
RC.