MT46V32M4TG-6T:D TR Micron Technology Inc, MT46V32M4TG-6T:D TR Datasheet - Page 10

• Manufacturer Part Number: MT46V32M4TG-6T:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V32M4TG-6T:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (32Mx4)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1024-2

Ball/Pin Descriptions and Assignments
Table 4:
09005aef8074a655
128MBDDRx4x8x16_2.fm - Rev. J 4/05 EN
M8, M2, L3,
L2, K3, K2,
K7, L8, L7,
Numbers
H7, G8,
G2, G3
J3, K8,
FBGA
J8, J7
H3
H8
G7
3F
J2
Ball/Pin Descriptions
29, 30, 31,
32, 35, 36,
37, 38, 39,
Numbers
23, 22,
45, 46
20, 47
26, 27
40, 28
TSOP
44
24
21
47
41
RAS#, CAS#,
A0, A1, A2,
A3, A4, A5,
A6, A7, A8,
LDM, UDM
BA0, BA1
Symbol
A9, A10,
CK, CK#
WE#
CKE
A11
CS#
DM
Input
Input
Input
Input
Input
Input
Input
Type
Description
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQ and DQS)
is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE
in any bank). CKE is synchronous for POWER-DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF
REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
level after V
after which it becomes a SSTL_2 input only.
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when
CS# is registered HIGH. CS# provides for external bank selection
on systems with multiple banks. CS# is considered part of the
command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. For the x16, LDM is DM for DQ0–
DQ7 and UDM is DM for DQ8–DQ15. Pin 20 is a NC on x4 and x8.
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10
HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
10
Ball/Pin Descriptions and Assignments
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
is applied and until CKE is first brought
128Mb: x4, x8, x16 DDR SDRAM
©2000 Micron Technology, Inc. All rights reserved.
HIGH,
LOW