Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 96

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

also the interrupt response sequence used for all internal interrupts
(except TRAP).
As depicted in Figure 41, the low-order byte of the vector table address
has the most significant three bits of the software programmable IL
register while the least significant five bits are a unique fixed value for
each interrupt (INT1, INT2 and internal) source:
Figure 41.
INT1 and INT2 are globally masked by IEF1 is
individually maskable by respectively clearing the ITE1 and ITE2 (bits
1,2) of the INT/TRAP control register to
During RESET, IEF1, ITE1 and ITE2 bits are reset to
Internal Interrupts
Internal interrupts (except TRAP) use the same vectored response mode
as INT1 and INT2. Internal interrupts are globally masked by IEF1 is
Individual internal interrupts are enabled/disabled by programming each
I
16-bit Vector
INT1, INT2 Vector Acquisition
IL
Fixed Code
(5 bits)
Vector + 1
Vector
of starting address
of starting address
High-order 8 bits
Low-order 8 bits
0
.
Memory
0
. Each is also
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
0
.
32 Bytes
Vector
Table
0
.
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