Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 77

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

62
MMU Bank Base Register (BBR: 39H)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position
7
–
Z 8018x Fam il y
M PU Us e r M anual
0
Bit/Field
BB7
BB7
R/W
–
7
MMU Bank Base Register (BBR)
BBR specifies the base address (on 4KB boundaries) used to generate a
20-bit physical address for Bank Area accesses. All bits of BBR are reset
to
Physical Address Translation
Figure 29 illustrates the way in which physical addresses are generated
based on the contents of CBAR, CBR and BBR. MMU comparators
classify an access by logical area as defined by CBAR. Depending on
which of the three potential logical areas (Common Area 1, Bank Area, or
Common Area 0) is being accessed, the appropriate 8- or 7-bit base
address is added to the high-order 4 bits of the logical address, yielding a
19- or 20-bit physical address. CBR is associated with Common Area 1
accesses. Common Area 0, if defined, is always based at physical address
00000H
0
0
0
during RESET.
R/W
R/W
BB6
R/W
.
6
0
Value Description
R/W
BB5
5
0
BBR specifies the base address (on 4KB boundaries) used
to generate a 20-bit physical address for Bank Area
accesses.
BB4
R/W
4
0
R/W
BB3
3
0
R/W
BB2
2
0
BB1
R/W
1
0
R/W
BB0
0
0