Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 123

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

108
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
DREQ0
TEND0
Phi
Phi
rising edge of the clock prior to T3 at which time the DMA operation
(re)starts. Figure 48 depicts the edge-sense DMA timing.
Figure 48.
During the transfers for channel 0, the TEND0 output goes Low
synchronous with the write cycle of the last (BCR0 =
(Reference Figure 49).
Figure 49.
The DREQ0 and TEND0 pins are programmably multiplexed with the
CKA0 and CKA1 ASCI clock input/outputs. However, when DMA
channel 0 is programmed for memory to/from I/O (and memory to/from
DMA
Write
Cycle
Tw
**
T1
T3
T1 T2
DMA read cycle
CPU
Machine
Cycle
CPU Operation and DMA Operation DREQ0 is Programmed
for Edge-Sense
TEND0 Output Timing Diagram
T2
**
T3
Last DMA cycle (BCR0 = 00H)
T3
T1
DMA
Read
Cycle
T2
T3
T1
T1
DMA write cycle
T2
T2
DMA
Write
Cycle
Tw
**
** DREQ0 is sampled at
T3
TW
T1
CPU
Machine
Cycle
T2
**
T3
T3
OOH
) DMA transfer