Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 48

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

INT1, NMI
.
A0
Figure 20.
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
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MREQ
HALT
–
A19
The internal CPU clock stops, reducing power consumption
The internal crystal oscillator does not stop
Internal and external interrupt inputs can be received
DRAM refresh cycles stop
I/O operations using on-chip peripherals continue
The internal DMAC stop
BUSREQ can be received and acknowledged
Address outputs go High and all other control signal outputs become
inactive High
Phi
RD
M1
HALT Op Code address
HALT Timing Diagram
T1
HALT Op Code
Fetch Cycle
T3
T1
HALT mode
HALT Op Code address + 1
T2
T3
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
T1
Interrupt
acknowledge cycle
T2
33