Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 147

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

132
ASCI Control Register B 0 (CNTLB0: 02H)
ASCI Control Register B 1 (CNTLB1: 03H)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
Z 8018x Fam il y
M PU Us e r M anual
MPBT
MP
MPBT
R/W
7
X
R/W
R/W
R/W
MP
6
0
Value
CTS/PS
R/W
5
0
Description
Multiprocessor Bit Transmit — When multiprocessor
communication format is selected (MP bit is 1), MPBT is
used to specify the MPB data bit for transmission. If
MPBT is 1, then MPB = 1 is transmitted. If MPBT is 0,
then MPBT = 0 is transmitted. MPBT state is undefined
during and after RESET.
Multiprocessor Mode — When MP is set to 1, the data
format is configured for multiprocessor mode based on
the MOD2 (number of data bits) and MOD0 (number of
stop bits) bits in CNTLA. The format is as follows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Multiprocessor (MP = 1) format has no provision for
parity. If MP is 0, the data format is based on MOD0
MOD1, MOD2, and may include parity. The MP bit is
cleared to 0 during RESET.
R/W
PE0
4
0
R/W
DR
3
0
R/W
SS2
2
1
R/W
SS1
1
1
R/W
SS0
0
1