Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 125

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

110
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
DREQ0 for ASCI transmission and reception respectively. To initiate
memory to/from ASCI DMA transfer, perform the following operations:
1. Load the source and destination addresses into SAR0 and DAR0
Table 16. DMA Transfer Request
Note: X = Don’ t care
Note: X = Don’ t care
DAR18
SAR18
Specify the I/O (ASCI) address as follows:
a. Bits A0–A7 must contain the address of the ASCI channel
b. Bits A8–A15 must equal 0.
c. Bits SAR17–SAR16 must be set according to Table 16 to enable
X
X
X
X
X
X
X
X
transmitter or receiver (I/O addresses
use of the appropriate ASCI status bit as an internal DMA
request.
DAR17
SAR17
0
0
1
1
0
0
1
1
DAR16 DMA Transfer Request
SAR16 DMA Transfer Request
0
1
0
1
0
1
0
1
DREQ0
RDRF (ASCI channel 0)
RDRF (ASCI channel 1)
Reserved
DREQ0
TDRE (ASCI channel O)
TDRE (ASCI channel 1)
Reserved
6H
-
9H
).