Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 69

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

54
UM005001-ZMP0400
Bit
Position Bit/Field
2
1
0
Z 8018x Fam il y
M PU Us e r M anual
LNIO
LNCPUCTL
LNAD/
DATA
Memory Management Unit (MMU)
The Z8X180 features an on-chip MMU which performs the translation of
the CPU 64KB (16-bit addresses
address space into a 1024KB (20-bit addresses
physical memory address space. Address translation occurs internally in
parallel with other CPU operation.
Logical Address Spaces
The 64KB CPU logical address space is interpreted by the MMU as
consisting of up to three separate logical address areas, Common Area 0,
Bank Area, and Common Area 1.
As depicted in Figure 23, a variety of logical memory configurations are
possible. The boundaries between the Common and Bank Areas can be
programmed with 4KB resolution.
R/W
R/W
R/W
R/W
Value Description
0
1
0
1
0
1
Standard Drive
33% Drive on certain external I/O
Standard Drive
33% Drive on CPU control signals
Standard Drive
33% drive on A10–A0, D7–D0
0000H
to
FFFFH
00000H
) logical memory
to
FFFFFH
)