Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 325

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Relative addressing
RETI
RTS0 timing diagram
S
Secondary bus interface
SLEEP mode
SLP execution cycle timing diagram
CSI/O control/status
Direct bit field definitions
DMA mode (DMODE)
DMA status
DMA/WAIT control
Flag
I/O Control
I/O control (ICR)
Indirect addressing
INT/TRAP control (ITC)
Interrupt Vector (I)
MMU bank base (BBR)
MMU common bank area (CBAR)
MMU common base (CBR)
Operation mode control
PRT timer control register
Refresh control
Addressing
control signal states
Instruction sequence
160, 161, 172
Relative
178
33
42
95
183
88
140
42
181
66
165
85
147, 150, 159,
84
100
97
15, 84
62
67
181
161
61
60
Status summary table
SYSTEM STOP mode
T
Test conditions, standard
Timer initialization, count down and reload
163
Timer output timing diagram
Timing diagram
Timing diagram
Timing diagram
AC
Bus Exchange Timing During CPU Inter-
Bus Exchange Timing During Memory
CPU (I/O Read/Write cycles)
CSI/O external clock receive
CSI/O external clock transmit
CSI/O internal clock receive
CSI/O internal clock transmit
CSI/O receive/transmit
CSI/O timer output
DCD0
DMA control signals
DMA CYCLE STEAL mode
DMA edge-sense
DMA level-sense
197
SLP execution cycle
Timer output
nal Operation
Read
139
26
163
MPU User Manual
10
108
202
107
27
UM005001-ZMP0400
35
164
Z8018x Family
205
200
204
203
155
156
106
199
153
154
309