Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 116

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

DMA/WAIT Control Register (DCNTL: 32H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
5
3
1
–
–
–
–
6
4
2
0
MWI1
IWI1
DMS1
DIM1
7
MWI1
R/W
0
–
–
–
0
–
0 R/W
0 R/W
0 R/W
R/W
6
MWI0
R/W
0
Value
5
IWI1
R/W
0
Description
Memory Wait Insertion — Specifies the number of wait
states introduced into CPU or DMAC memory access
cycles. MWI1 and MWI0 are set to 1 during RESET. See
section on Wait State Generator for details.
Wait Insertion — Specifies the number of Wait States
introduced into CPU or DMAC I/O access cycles. IWI1
and IWI0 are set to 1 during RESET. See section on Wait
State Generator for details.
DMA Request Sense — Specifies the DMA request
sense for channel 0 (DREQ0) and channel 1 (
respectively. When reset to 0, the input is level-sense.
When set to 1, the input is edge-sense.
DMA Channel 1 I/O and Memory Mode — Specifies
the source/destination and address modifier for channel 1
memory to/from I/O transfer modes. Reference Table 15.
4
IWI0
R/W
0
3
DMS1
R/W
0
2
DMS0
R/W
0
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
1
DIM1
R/W
0
DREQ
0
DIM0
R/W
0
1)
101