Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 326

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

310
UM005001-ZMP0400
Z8018x Family
MPU User Manual
DMA TEND0 output
E clock (memory and I/O R/W cycles)
E clock (R/W and INTACK cycles)
E clock (SLEEP and SYSTEM STOP
E clock BUS RELEASE, SLEEP and SYS-
E clock minimum timing example of
External clock rise and fall
HALT
I/O Read and Write cycles with IOC = 0
I/O read and write cycles with IOC=1
I/O read/write timing
Input rise and fall time
Instruction
INT0 interrupt mode 2
INT0 mode 0
INT0 mode 1
INT1, INT2 and Internal interrupts
M1 temporary enable
Memory read/write timing (with Wait
Memory read/write timing (without Wait
NMI and DMA operation
Op Code Fetch timing (with Wait state)
Op Code Fetch timing (without Wait state)
PRT bus release mode
Refresh cycle
RESET
RTS0
modes)
TEM STOP modes)
PWEL and PWEH)
state)
state)
19
140
33
25
22
21
24
168
76
78
87
23
108
16
167
204
80
202
201
115
204
86
167
201
17
17
20
TRAP
U
Undefined Fetch Object (UFO)
V
Vector acquisition
Vector table
W
Wait state generation
Wait state insertion
SLEEP
TRAP timing - 2nd Op Code Undefined
TRAP timing - 3rd Op Code Undefined
WAIT
Interrupt
Timing
INT0 mode 2
INT1, INT2
I/O Wait insertion
Memory and
Programmable Wait state insertion
Wait input and reset
68
28
35
71
82
70
81
29
79
30
29
30
68
28
71
72