Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 34

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

The Op Code on the data bus is latched at the rising edge of T3 and the
bus cycle terminates at the end of T3.
Figure 9.
Figure 10 illustrates the insertion of Wait States (TW) into the Op Code
fetch cycle. Wait States (TW) are controlled by the external WAIT input
combined with an on-chip programmable Wait State generator.
At the falling edge of T2 the combined WAIT input is sampled. If WAIT
input is asserted Low, a Wait State (TW) is inserted. The address bus,
MREQ, RD and M1 are held stable during Wait States. When WAIT is
sampled inactive High at the falling edge of TW, the bus cycle enters T3
and completes at the end of T3.
A0
D0
MREQ
WAIT
–
–
A19
Phi
RD
M1
D7
Op Code Fetch (without Wait State) Timing Diagram
T1
T2
T3
T1
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
T2
19