Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 321

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

A
AC characteristics
Address generation, physical
Address map
Addressing
Architecture
ASCI
Asynchronous serial communications interface
(ASCI)
I/O
I/O address translation
Logical examples
Logical memory organization
Logical space configuration
Physical address transition
Extended
I/O
Indexed
Indirect
Baud rate selection
Block diagram
Clock diagram
Control register A0
Control register A1
Control register B
Functions
Interrupt request circuit diagram
Register descriptions
Status register 0
Status register 1
14
44
184
181
182
12
182
116
197
117
141
120
123
55
131
142
125
128
117
57
64
56
59
58
140
B
Baud rate selection
Block diagram
Bus state controller
C
Central processing unit (CPU)
Circuit diagram, ASCI interrupt request
Clock generator
Clocked serial I/O (CSI/O)
CPU register configurations
CPU timing
ASCI
CSI/O
ASCI
CSI/O
DMAC
MMU
PRT
Basic instruction
BUSREQ/BUSACK Bus Exchange
HALT and Low Power modes
I/O data read/write
Internal I/O registers
MMU register description
Op Code fetch timing
Operand and data read/write
RESET
Wait state generator
157
142
117
56
150
146
92
25
6
13
13
MPU User Manual
23
UM005001-ZMP0400
22
27
Z8018x Family
41
18
14
176
14
60
20
31
140
25
305