Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 59

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

44
Table 6.
UM005001-ZMP0400
ASCI
CSI/O
Z 8018x Fam il y
M PU Us e r M anual
Register
ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
CSI/O Control Register
CSI/O Transmit/Receive Data Register TRD
I/O Address Map for Z80180-Class Processors Only
address to
OTDMR and TSTIO (see Instruction Set).
When writing to an internal I/O register, the same I/O write occurs on the
external bus. However, the duplicate external I/O write cycle exhibits
internal I/O write cycle timing. For example, the WAIT input and
programmable Wait State generator are ignored. Similarly, internal I/O
read cycles also cause a duplicate external I/O read cycle. However, the
external read data is ignored by the Z8X180.
Normally, external I/O addresses should be chosen to avoid overlap with
internal I/O addresses and duplicate I/O accesses.
0
. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM,
CNTLA0
CNTLA1
CNTLB0
CNTLB1
STAT0
STAT1
TDR0
TDR1
RDR0
RDR1
CNTR
Mnemonic
XX000000
XX000001
XX000010
XX000011
XX000100
XX000101
XX000110
XX000111
XX001000
XX001001
XX001010
XX1011
Binary
Address
0AH
0BH
Hex
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
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