Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 22

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Z 8018x Fam il y
M PU Us e r M anual
7
PIN DESCRIPTION
A0–A19. Address Bus (Output, Active High, 3-state). A0–A19 form a 20-
bit address bus. The Address Bus provides the address for memory data
bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The
address bus enters a high impedance state during RESET and external bus
acknowledge cycles. Address line A18 is multiplexed with the output of
PRT channel 1 (TOUT, selected as address output on RESET) and
address line A19 is not available in DIP versions of the Z8X180.
BUSACK . Bus Acknowledge (Output, Active Low). BUSACK indicates
that the requesting device, the MPU address and data bus, and some
control signals, have entered their high impedance state.
BUSREQ. Bus Request (Input, Active Low). This input is used by
external devices (such as DMA controllers) to request access to the
system bus. This request has a higher priority than NMI and is always
recognized at the end of the current machine cycle. This signal stops the
CPU from executing further instructions and places the address and data
buses, and other control signals, into the high impedance state.
CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, Active High).
These pins are the transmit and receive clocks for the ASCI channels.
CKA0, is multiplexed with DREQ0 and CKA1 is multiplexed with
TEND0.
CKS. Serial Clock (Bidirectional, Active High). This line is the clock for
the CSIO channel.
CLOCK (PHI). System Clock (Output, Active High). The output is used
as a reference clock for the MPU and the external system. The frequency
of this output is equal to one-half that of the crystal or input clock
frequency.
CTS0, CTS1. Clear to Send 0 and 1 (Inputs, Active Low). These lines are
modem control signals for the ASCI channels. CTS1 is multiplexed with RXS.
UM005001-ZMP0400