Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 181

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

166
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
These devices require connection with the Z8X180 synchronous E clock
output. The speed (access time) required for the peripheral devices are
determined by the Z8X180 clock rate. Table 24, and Figure 67 through
Figure 70 define E clock output timing.
Wait States are inserted in Op Code fetch, memory read/write, and I/O
read/write cycles which extend the duration of E clock output High.
During I/O read/write cycles with no Wait States (only occurs during on-
chip I/O register accesses), E does not go High.
Table 24. E Clock Timing in Each Condition
Condition
Op Code Fetch Cycle
Memory Read/Write Cycle
I/O read Cycle
I/O Write Cycle
NMI Acknowledge 1st MC
INT0 Acknowledge 1st MC
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Note: nw = the number of Wait States; MC: Machine Cycle
Duration of E Clock Output High
T2 rise - T3 fall
1st Tw rise - T3 fall
1st Tw rise - T3 rise
T2 rise - T3 fall
1st Tw rise - T3 fall
Phi fall - Phi fall
(1.5 Phi + nw x Phi)
(0.5Phi + nw x Phi)
In
(1.5 Phi)
(0.50 + nw x Phi
(2 Phi or 1 Phi)
w
x Phi)