Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 117

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

102
DMA I/O Address Register Ch. 1 (IAR1B: 2DH) (Z8S180/L180-Class Processor Only)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
7
6
5
3
–
Z 8018x Fam il y
M PU Us e r M anual
4
Reserved
7
R/W
0
Table 15. Channel 1 Transfer Mode
DIM1
0
0
1
1
R/W
6
R/W
R/W
R/W
R/W
R/W
0
DIM0
0
1
0
1
Value Description
5
0
1
0
0
1
Transfer Mode
Memory
Memory
I/O
I/O
to
to
Reserved
Alternating Channels
DMA Channels are independent
Toggle between DMA channels for same device
Currently selected DMA channel when Bit 7 = 1
Reserved. Must be 0.
TOUT/DREQ is DREQ In
TOUT/DREQ is TOUT Out
R/W
Memory
Memory
0
to
to
4
I/O
I/O
3
R/W
0
Address Increment/Decrement
MARI +1, IAR1 fixed
MARI -1, IAR1 fixed
IAR1 fixed, MAR1+1
IAR1 fixed, MAR1-1
2
1
R/W
0
0