Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 323

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Extended addressing
External clock rise and fall time
F
Features
H
HALT mode
I
I/O
I/O control register
Immediate addressing
Indexed addressing
Indirect addressing
Input ris and fall time (except EXTAL and RE-
SET) timing diagram
Instruction set
Timing diagram (SLEEP and SYSTEM
Addressing
Control register (ICR)
Addressing
CPU registers
Flag register
Summary
cles)
STOP modes)
Immediate
1
31
167
173
184
178
175
181
42
182
183
182
204
168
42
204
INT0
INT0 mode 0 timing
Interrupt
IOSTOP mode
L
Level-sense programming
Logical memory organization
M
M1 temporary enable timing
Maskable interrupt level 0
Interrupt mode 2 timing
Mode 1 interrupt sequence
Mode 1 timing
Acknowledge cycle timings
Control registers and flags
Controller
CSI/O request generation
DMA request generation
Enable (ITE)
INT/TRAP control register (ITC)
Maskable interrupt 0 (INT0)
Non-maskable
PRT request generation
Sources
Sources during reset
TRAP
Vector register (I)
70
65
13
35
68
72
78
MPU User Manual
76
66
UM005001-ZMP0400
83
Z8018x Family
109
75
164
80
16
114
58
151
65
77
82
75
67
307