Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 115

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

100
UM005001-ZMP0400
DM1 DM0 SM1 SM0 Transfer Mode
1
1
1
1
Note: *: includes memory mapped I/O.
Z 8018x Fam il y
M PU Us e r M anual
1
1
1
1
0
0
1
1
Table 14. Transfer Mode Combinations
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of Wait States into DMAC (and CPU)
accesses of memory or I/O Also, the DMA request mode for each DREQ
DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
0
1
0
1
Memory
Memory
Reserved
Reserved
to
to
I/O
I/O
Increment/Decrement
SAR0+1, DAR0 fixed
SAR0-1, DAR0 fixed