Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 103

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

88
Refresh Control Register (RCR: 36H)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
1
–
Z 8018x Fam il y
M PU Us e r M anual
0
REFE
REFW
CYC1
REFE
R/W
Refresh Control Register (RCR)
The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.
7
–
1
0 R/W
R/W
R/W
REFW
R/W
6
1
Value
0
1
0
1
5
Description
REFE: Refresh Enable
Disables the refresh controller
Enables refresh cycle insertion.
Refresh Wait (bit 6)
Causes the refresh cycle to be two clocks in duration.
Causes the refresh cycle to be three clocks in duration by
adding a refresh wait cycle (TRW).
Cycle Interval — CYC1 and CYC0 specify the interval
(in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms
(or 256 cycles in every 4 ms), the required refresh interval
is less than or equal to 15.625 s. Thus, the underlined
values indicate the best refresh interval depending on
CPU clock frequency. CYC0 and CYC1 are cleared to 0
during RESET. Refer to Table 11.
4
?
?
?
3
2
CYC1
R/W
1
0
CYC0
R/W
0
0