Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 38

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

A0
D0
WAIT
IORQ
–
–
A19
WR
Phi
RD
D7
T1
Figure 13.
Basic Instruction Timing
An instruction may consist of a number of machine cycles including Op
Code fetch, operand fetch, and data read/write cycles. An instruction may
also include cycles for internal processes which make the bus IDLE. The
example in Figure 14 illustrates the bus timing for the data transfer
instruction LD (IX+d),g.
I/O address
T2
I/O Read Cycle
I/O Read/Write Timing Diagram
TW
Read data
T3
T1
Write data
I/O Write Cycle
I/O address
T2
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
TW
T3
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