Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 8

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

List of Figures
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Figure 11. Memory Read/Write (without Wait State)
Figure 12. Memory Read/Write (with Wait State)
Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27
Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory and I/O Wait State Insertion
Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Op Code Fetch (without Wait State) Timing Diagram . . . .19
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
MPU User Manual
UM005001-ZMP0400
Z8018x Family
ix