Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 132

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

TXA0
RXA0
RTS0
CTS0
DCD0
Figure 52.
ASCI Register Description
The following subparagraphs explain the various functions of the ASCI
registers.
ASCI Transmit Shift Register 0, 1 (TSR0, 1)
When the ASCI Transmit Shift Register receives data from the ASCI
Transmit Data Register (TDR), the data is shifted out to the TXA pin.
ASCI Transmit Shift Register*
ASCI Transmit Data Register
ASCI Receive Shift Register*
ASCI Control Register A
ASCI Receive Data Register
ASCI Control Register B
ASCI Status Register
ch 0 : CNTLA0 (8)
ch 0 : STAT0 (8)
ch 0 : CNTLB0 (8)
ch 0 : RSR0 (8)
ch 0 : TSR0
ch 0 : TDR0
ch 0 : RDR0
ASCI Block Diagram
CKA1
CKA0
Internal Address/Data Bus
Interrupt Request
Generator 0
Generator 1
Baud Rate
Baud Rate
Control
ASCI
ASCI Transmit Data Register
ASCI Transmit Shift Register*
ASCI Receive Data Register
ASCI Receive Shift Register*
ASCI Control Register B
ASCI Control Register A
ASCI Status Register
ch 1 : CNTLB1 (8)
ch 1 : CNTLA1 (8)
ch 1 : STAT1 (8)
Phi
ch 1 : RSR1 (8)
ch 1 : TDR1
ch 1 : RDR1
* Not program Accessible
ch 1 : TSR1
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
TXA1
RXA1
CTS1
117