Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 25

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

10
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
RTS0. Request to Send 0 (Output, Active Low). This output is a
programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals
are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (Input, Active High). This line is the
receiver data for the CSIO channel. RXS is multiplexed with the CTS1
signal for ASCI channel 1.
ST. Status (Output, Active High). This signal is used with the M1 and
HALT output to decode the status of the CPU machine cycle. Table 1
provides status summary.
Table 1.
TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This
output is asserted active during the last write cycle of a DMA operation. It
is used to indicate the end of the block transfer. TEND0 in multiplexed
with CKA1.
TEST. Test (Output, not on DIP version). This pin is for test and must be
left open.
ST
0
1
1
0
0
1
1. X = Don't care
2. MC = Machine cycle
HALT
1
1
1
X
0
0
1
Status Summary
M1
0
0
1
1
0
1
Operation
CPU operation (1st Op Code fetch)
CPU operation (2nd Op Code and 3rd Op Code fetch)
CPU operation (MC
DMA operation
HALT mode
SLEEP mode (including SYSTEM STOP mode)
2
except for Op Code fetch)