Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 39

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

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UM005001-ZMP0400
A0
Z 8018x Fam il y
M PU Us e r M anual
D0
MREQ
–
Machine Cycle
–
A19
WR
Phi
RD
M1
D7
NOTE: d = displacement
T1 T2 T3 T1
g = register contents
1st Op Code
Fetch Cycle
Figure 14.
This instruction moves the contents of a CPU register (g) to the memory
location with address computed by adding a signed 8-bit displacement (d)
to the contents of an index register (IX).
The instruction cycle begins with the two machine cycles to read the two
byte instruction Op Code as indicated by M1 Low. Next, the instruction
operand (d) is fetched.
MC1
PC
(DDH)
2nd Op Code
Fetch Cycle
Instruction Timing Diagram
(7OH
T2
MC2
PC+1
–
T3 T1
77H)
Displacement
Read Cycle
T2 T3 T1 T1 T1 T1
MC3
d
PC+2
MC4 MC5 MC6
CPU internal
Operation
Memory
Write Cycle
T2 T3
MC7
IX+d
g
T1
Next instruction
Fetch Cycle
PC+3
T2