Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 45

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

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Table 4.
UM005001-ZMP0400
Note:
1.
2.
I W I 1
Z 8018x Fam il y
M PU Us e r M anual
0
0
1
1
For Z8X180 internal I/O register access (I/O addresses
determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States
(TW) are generated. The number of Wait States inserted during access to these registers is a function of
internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is,
MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only
three clock cycles.
For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC
stacking cycle, memory access timing applies.
I W I 0
0
1
0
1
Wait State Insertion
For e xt e rnal
acce s s e s
I / O re gis t e rs
inserted depending on the programmed value in IWI1 and IWI0. Refer to
Table 4.
WAIT Input and RESET
During RESET, MWI1, MWI0 IWI1 and IWI0, are all
maximum number of Wait States (TW) (three for memory accesses, four
for external I/O accesses).
1
2
3
4
For int e rnal
I / 0
re gis t e rs
acce s s e s
(Note 1)
0
Th e Num be r of W ait St ate s
For I NT0
int e rrupt
ack now l e dge
cycl e s w h e n
M 1 is L ow
0000H
2
4
5
6
-
003FH
For I NT1,
I NT2 and
int e rnal
int e rrupts
ack now l e dge
cycl e s
(Note 2)
), IWI1 and IWI0 do not
2
1
, selecting the
For NM I
int e rrupt
ack now l e dge
cycl e s
w h e n M 1 is
L ow
(Note 2)
0