Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 165

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

150
CSI/O Transmit/Receive Register (TRDR: 0BH)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Z 8018x Fam il y
M PU Us e r M anual
7
Table 22. CSI/O Baud Rate Selection
After RESET, the CKS pin is configured as an external clock input (SS2,
SS1, SS0 = 1). Changing these values causes CKS to become an output pin
and the selected clock is output when transmit or receive operations are
enabled.
CSI/O Interrupts
The CSI/O interrupt request circuit is shown in Figure 58.
Note: ( ) indicates the baud rate (BPS) at Phi = 4 MHz.
SS2
0
0
0
0
1
1
1
1
6
SS1
0
0
1
1
0
0
1
1
5
CSI/O Transmit/Receive Data
SS0
0
1
0
1
0
1
0
1
4
Divide Ratio
External Clock input (less than
R/W
20
40
80
160
320
640
1280
0
3
2
Baud Rate
(200000)
(100000)
(50000)
(25000)
(12500)
(6250)
(3125)
1
20)
0