Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 27

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

12
ARCHITECTURE
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
Table 2.
The Z8X180 combines a high performance CPU core with a variety of
system and I/O resources useful in a broad range of applications. The CPU
core consists of five functional blocks: clock generator, bus state controller
(including dynamic memory refresh), interrupt controller, memory
management unit (MMU), and the central processing unit (CPU). The
integrated I/O resources make up the remaining four functional blocks:
•
•
Multiplexed
Pins
A18/TOUT
CKA0/
CKA1/
RXS/
Direct Memory Access (DMA) Control (2 channels)
Asynchronous Serial Communications Interface (ASCI, 2 channels),
CTS1
DREQ0
TEND0
Multiplexed Pin Descriptions
Descriptions
During RESET, this pin is initialized as A18 pin. If either
TOC1 or TOC0 bit of the Timer Control Register (TCR) is
set to 1, TOUT function is selected. If TOC1 and TOC0 bits
are cleared to 0, A18 function is selected.
During RESET, this pin is initialized as CKA
If either DM1 or SM1 in DMA Mode Register (DMODE) is
set to 1,
During RESET, this pin is initialized as CKA1 pin. If
CKA1D bit in ASCI control register ch 1 (CNTLA1) is set to
1,
CKA1 function is selected.
During RESET, this pin is initialized as RXS pin. If CTS1E bit
in ASCI status register ch 1 (STAT1) is set to 1,
is selected. If CTS1E bit is 0, RXS function is selected.
TEND0
DREQ0
function is selected. If CKA1D bit is set to 0,
function is always selected.
0
CTS1
pin.
function