Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 297

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Request
WAIT
Refresh Request
Request of Refresh
by the on-chip
Refresh Controller
DREQ0
DREQ1
BUSREQ
Interrupt INT0,
INT1,
1NT2
Current
Status
Normal
Operation
(CPU mode
and IOSTOP
Mode)
Acceptable
Refresh cycle
begins at the
end of Machine
Cycle (MC)
DMA cycle
begins at the
end of MC
Bus is released
at the end of
MC
Accepted after
executing the
current
instruction.
Table 53. Request Acceptances in Each Operating Mode
WAIT State
Acceptable
Not
acceptable
DMA cycle
begins at the
end of MC
Not
acceptable
Accepted
after
executing the
current
instruction
Refresh
Cycle
Not
acceptable
Not
acceptable
Acceptable
Refresh cycle
precedes.
DMA cycle
begins at the
end of one
MC
Not
acceptable
Not
acceptable
Interrupt
Acknowledge
Cycle
Acceptable
Refresh cycle
begins at the
end MC
Acceptable
DMA cycle
begins at the
end of MC.
Bus is released
at the end of
MC
Not
acceptable
DMA Cycle
Acceptable
Refresh cycle
begins at the
end of MC
Acceptable
Refer to
“DMA
Controller”
for details.
Bus is
released at the
end of MC
Not
acceptable
BUS
RELEASE
Mode
Not
acceptable
Not
acceptable
Acceptable
*After BUS
RELEASE
cycle, DMA
cycle begins
at the end of
one MC
Continue
BUS
RELEASE
mode
Not
acceptable
MPU User Manual
UM005001-ZMP0400
Z8018x Family
SLEEP
Mode
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable Acceptable
Acceptable
Return from
SLEEP
mode to
normal
operation.
SYSTEM
STOP
Mode
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Return from
SYSTEM
STOP mode
to normal
operation
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