Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 140

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

ASCI Control Register A 0 (CNTLA0: 00H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
MPE
MPE
R/W
7
0
ASCI Control Register A0, 1 (CNTLA0, 1)
Each ASCI channel Control Register A configures the major operating
modes such as receiver/transmitter enable and disable, data format, and
multiprocessor communication mode.
R/W
R/W
RE
6
0
Value
R/W
TE
5
0
Description
Multi-Processor Mode Enable — The ASCI has a
multiprocessor communication mode which utilizes an
extra data bit for selective communication when a number
of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set
to 1. If multiprocessor mode is not selected (MP bit in
CNTLB = 0), MPE has no effect. If multiprocessor mode
is selected, MPE enables or disables the wakeup feature
as follows. If MPE is set to 1, only received bytes in
which the MPB (multiprocessor bit) is 1 can affect the
RDRF and error flags. Effectively, other bytes (with MPB
is 0) are ignored by the ASCI. If MPE is reset to 0, all
bytes, regardless of the state of the MPB data bit, affect
the RDRF and error flags.
RTS0
R/W
4
1
MPBR/
EFR
R/W
3
X
MOD2
R/W
2
0
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
MOD1
R/W
1
0
MOD0
R/W
0
0
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