peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 96

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

The user defined loop up and loop down pattern is programmable individually from 2 to
8 bit in length (LCR1.LAC1/0 and LCR1.LDC1/0). Programming of loop codes is done in
registers LCR2 and LCR3.
Status and interrupt status bits inform the user whether a loop up or loop down code was
detected.
4.5.7
The transparent modes are useful for loopbacks or for routing data unchanged through
the FALC
In receive direction, transparency for ternary or dual/single rail unipolar data is always
achieved if the receiver is in the synchronous state. In asynchronous state the data may
be transparently switched through if bit FMR2.DAIS is set. However, correct time slot
assignment can not be guaranteed due to missing frame alignment between line and
system side.
Setting of bit FMR2.RTM disconnects control of the internal elastic store from the
receiver. The elastic buffer is now in a “free running” mode without any possibility to
update the time slot assignment to a new frame position in case of re-synchronization of
the receiver. Together with FMR2.DAIS this function can be used to realize undisturbed
transparent reception.
Transparency in transmit direction can be achieved by activating the time slot 0
transparent mode (bit XSP.TT0 or TSWM.7-0). If XSP.TT0 = 1 all internal information of
the FALC
TSWM the S
transparent from port XDI to the far end. For complete transparency the internal signaling
controller, IDLE code generation and AIS alarm generation, single channel and payload
loop back has to be disabled.
Data Sheet
®
®
-LH.
-LH (framing, CRC, S
Time Slot 0 Transparent Mode
i
-bits, A-bit or the S
a
/S
a
i
4-8 bits can be selectively enabled to send data
bit signaling, remote alarm) is ignored. With register
96
Functional Description E1
FALC-LH V1.3
PEB 2255
2000-07