peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 243

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC Error Counter 3 (Read)
CE15…0…
Data Sheet
CEC3H
CEC3L
CE15
CE7
7
7
CRC Error Counter (detected at T Ref. Point via Sa6 -Bit)
If doubleframe format is selected, CEC3H/L has no function. If CRC-
multiframe mode is enabled, CEC3H/L works as SA6 Bit error
indication counter (16 bits) which counts the SA6 Bit sequence 0010
and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
SA6 Bit sequence: SA6
SA6
Clearing and updating the counter is done according to bit
FMR1.ECM.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC3
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCEC3 is reset
automatically with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
1
is received in frame 1 or 9 in every multiframe.
243
1
, SA6
2
, SA6
3
, SA6
4
= 0010 or 0011 where
FALC-LH V1.3
CE0
CE8
E1 Registers
0
0
PEB 2255
2000-07
(5A)
(5B)