peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 206

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive Control 1 (Read/Write)
Value after RESET: 00
SWD …
ASY4 …
RTO5...0…
Data Sheet
RC1
SWD
7
Service Word Condition Disable
0…
1…
0…
1…
Receive Time Slot Offset/Receive Frame Marker Offset
Depending on bit SIC2.SRFSO this bit enables different functions:
Receive Time Slot Offset (SIC2.SRFSO = 0)
Initial value which is loaded into the receive time slot counter at the
trigger edge of SCLKR when the synchronous pulse on port SYPR is
active.
Receive Frame Marker Offset (SIC2.SRFSO = 1)
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker could be activated during any
bit position of the current frame.
Calculation of the value X of the “Receive Counter Offset” register
RC1/0 depends on the bit position BP which should be marked and
SCLKR:
X = (2 + 2 BP) mod 512, for SCLKR = 2.048 MHz.
Select Loss of Sync Condition
ASY4
H
Standard operation. Three or four consecutive incorrect service
words (depending on bit RC1.ASY4) causes loss of
synchronization.
Errors in service words have no influence when in synchronous
state. However, they are used for the resynchronization
procedure.
Standard operation. Three consecutive incorrect FAS words or
three consecutive incorrect service words causes loss of
synchronization.
Four consecutive incorrect FAS words or four consecutive
incorrect service words causes loss of synchronization. The
service word condition may be disabled via bit RC1.SWD.
RTO5
RTO4
206
RTO3
RTO2
RTO1
FALC-LH V1.3
RTO0
E1 Registers
0
PEB 2255
2000-07
(23)