peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 297

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Loop Code Register 1 (Read/Write)
Value after RESET: 00
EPRM…
XPRBS…
LDC1…0...
Data Sheet
LCR1
EPRM
7
XPRBS
0…
1…
A one in this bit position enables transmitting of a pseudo random bit
sequence to the remote end. Depending on pit LLBP the PRBS is
generated according to 2
These bits defines the length of the LLB deactivate code which is
programmable in register LCR2.
00… length: 5 bit
01… length: 6 bit
10… length: 7 bit
11… length: 8 bit
If a shorter pattern length is required, select a multiple of the required
Enable Pseudo Random Bit Sequence Monitor
Transmit Pseudo Random Bit Sequence
Length Deactivate (Down) Code
H
Pseudo random bit sequence (PRBS) monitor is disabled.
PRBS monitor is enabled. Setting this bit enables incrementing
the CEC2 error counter with each detected PRBS bit error. With
any change of state of the PRBS internal synchronization
status an interrupt ISR1.LLBSC is generated. The current
status of the PRBS synchronizer is indicated by bit
FRS1.LLBAD. The expected PRBS sequence has to be
selected by bit LCR1.LLBP.
The PRBS status signal is output on pin RFSP, if XC0.SFRZ=1
and LCR1.EPRM=1. It is set high, if the PRBS monitor is in
synchronous state.
length and repeat the pattern in LCR2.
LDC1
LDC0
297
15
LAC1
-1 or 2
20
LAC0
-1 ( ITU-T O. 151).
FLLB
FALC-LH V1.3
T1/J1 Registers
LLBP
0
PEB 2255
2000-07
(39)