peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 152

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

5.5.9
The FALC
which is defined by ANSI T1. 403. More than 15 consecutive zeros or less than 23 ones
in each and every time window of 193 data bits are detected. Violations of these rules
are indicated by setting the status bit FRS1.PDEN and the interrupt status bit
ISR0.PDEN. Generation of the interrupt status may be programmed either with the
detection or with any change of state of the pulse density alarm (GCR.SCI).
5.6
5.6.1
The FALC
bit sequences (PRBS). The generated PRBS pattern is transmitted optionally inverted or
not to the remote end via pins XL1/2 or XDOP/N. Generating and monitoring of PRBS
pattern is done according to ITU-T O. 151 and TR62411 with maximum 14 consecutive
zero restriction.
The PRBS monitor senses the PRBS pattern in the incoming data stream.
Synchronization is done on the inverted and non inverted PRBS pattern. The current
synchronization status is reported in status and interrupt status registers. Enabled by bit
LCR1.EPRM each PRBS bit error increments an error counter (BEC). Synchronization
is reached within 400 ms with a probability of 99.9% and a BER of 1/10 (pattern defined
by ITU-T O.151).
Data Sheet
®
®
Pulse Density Detection
Test Functions (T1/J1)
Pseudo-Random Bit Sequence Generation and Monitor
-LH has the ability to generate and monitor a 2
-LH examines the receive data stream on the pulse density requirement
152
Functional Description T1/J1
15
-1 and 2
20
-1 pseudo-random
FALC-LH V1.3
PEB 2255
2000-07