peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 225

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

DAF…
Disable Error Counter (Write)
Value after RESET: 00
DCEC3…
DCEC2…
DCEC1…
DEBC …
DCVC…
DFEC…
Data Sheet
DEC
7
Disable Automatic Freeze
Valid only if serial signaling access is enabled.
0…
1…
Disable CRC Error Counter 3
Disable CRC Error Counter 2
Disable CRC Error Counter
These bits are only valid if FMR1.ECM is cleared. They have to be set
before reading the error counters. They are reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of these bits the error counters are latched and then cleared.
Disable Errored Block Counter
Disable Code Violation Counter
Disable Framing Error Counter
H
Signaling is automatically frozen if one of the following alarms
occurred: Loss of Signal (FRS0.LOS), Loss of CAS Frame
Alignment (FRS1.TS16LFA) or receive slips (ISR3.RSP/N).
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer is
stopped if SIC2.FFS is set.
DCEC3 DCEC2 DCEC1
225
DEBC
DCVC
FALC-LH V1.3
DFEC
E1 Registers
0
PEB 2255
2000-07
(60)