peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 84

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

•
Table 18
Enabled by
–
XSP.TT0
TSWM.TSIF
TSWM.TSIS
TSWM.TRA
TSWM.TSA4-8
1)
2)
3)
•
Figure 25
4.4.2.2
Synchronization status is reported via bit FRS0.LFA. Framing errors are counted by the
Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4
consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0
in time slot 0 of every other frame not containing the frame alignment word), the selection
is done via bit RC1.ASY4. Additionally, the service word condition can be disabled.
When the framer lost its synchronization an interrupt status bit ISR2.LFA is generated.
In asynchronous state, counting of framing errors and detection of remote alarm is
stopped. AIS is automatically sent to the backplane interface (can be disabled via bit
FMR2.DAIS).
Further on the updating of the registers RSA6S and RS1-16 is halted (remote alarm
indication, S
Data Sheet
pin XDI or XSIG or XFIFO-Buffer (signaling controller)
Additionally, automatic transmission of the A-bit is selectable
As a special extension for double frame format, the Sa-bit register may be used optionally.
XSIG
XDI
Synchronization Procedure
a
SIC3.TTRF
/S
TTR1...4
Transmit Transparent Mode (Doubleframe E1)
Data Flow in Transparent Mode
i
-Bit access).
Framing
(int. generated)
via pin XDI
(int. generated)
(int. generated)
(int. generated)
(int. generated)
Framing
Transmit Transparent Source for
1)
XSW
A Bit
XSW.XRA
via pin XDI
XSW.XRA
XSW.XRA
via pin XDI
XSW.XRA
Service Word
TSWM bits
84
2)
XSA8 ... 4
S
XSW.XY0 … 4
via pin XDI
XSW.XY0 … 4
XSW.XY0 … 4
XSW.XY0 … 4
via pin XDI
a
Bits
FMR1.ENSA
Functional Description E1
3)
S
XSW.XSIS,XSP.XSIF
via pin XDI
via pin XDI
via pin XDI
XSW.XSIS,XSP.XSIF
XSW.XSIS,XSP.XSIF
i
Bits
FALC-LH V1.3
TT0
PEB 2255
2000-07
XL1/2
F0059