peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 190

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RADD…
RCRC…
XCRC…
Preamble Register (Read/Write)
Value after RESET: 00
PRE7...0…
Note: Zero bit insertion is disabled during preamble transmission.
Data Sheet
PRE
7
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. See
description.
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO by the status information
byte (contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “Valid Frame” check are modified (refer to RSIS.VFR
and to
Transmit CRC ON/OFF
If this bit is set, the CRC checksum is not generated internally. It has
to be written as the last two bytes in the transmit FIFO (XFIFO). The
transmitted frame is closed automatically with a closing flag.
Note: The FALC
This register defines the pattern which is sent during preamble
transmission (refer to CCR3). LSB is sent first.
Receive Address Pushed to RFIFO
Receive CRC ON/OFF
Preamble Register
H
Chapter 8.1
frame, i.e. the number of bytes to be transmitted makes sense
or not.
®
-LH does not check whether the length of the
on page 169).
190
Chapter 8.1
on page
169
FALC-LH V1.3
E1 Registers
0
for detailed
PEB 2255
2000-07
(0B)