peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 316

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Framing Error Counter (Read)
FE15…0…
Data Sheet
FECH
FECL
FE15
FE7
7
7
Framing Errors
This 16-bit counter is incremented when incorrect FT and FS bits in
F4, F12 and F72 format or incorrect FAS bits in ESF format are
received.
Framing errors are counted during basic frame synchronous state
only (but even if multiframe synchronous state is not reached yet).
The error counter doesn’t roll over. During alarm simulation, the
counter is incremented twice.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DFEC has
to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DFEC is reset automatically
with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
316
FALC-LH V1.3
T1/J1 Registers
FE0
FE8
0
0
PEB 2255
2000-07
(50)
(51)