peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 199

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Channel Loop Back Register (Read/Write)
Value after RESET: 00
SPN…
SFM…
Data Sheet
LOOP
SPN
7
Together with bit LIM3.ESY the functionality of pin 80 is defined:
Programming of LOOP.SPN and LIM3.ESY and the corresponding
pin function is shown below.
SPN/ESY:
Single Frame Mode
Setting this bit reduces the receive speech memory from two to one
frame length. In this case, clocks SCLKR and RCLK have to be phase
locked to avoid slip conditions. However, slip detection still works but
without any influence on data transmission.
Select Additional Optical Pin Functions
Note:This mode is not recommended, but possible to be compatible
SFM
H
00… function of pin 80 XSIG: If SIC3.TTRF = 1, transmit data
from the system interface. Internal multiplexing with the XDI
data stream is controlled by XSIGM. No input function defined
for SIC3.TTRF = 0.
01… function of pin 80 SYNC2: external synchronization input
for the DCO-X circuitry
10… function of pin 80 ROID: Receive Optical Interface Data
(Input) and Pin 68: XMFB/XOID Transmit Optical Interface Data
(Output). At the same time data received on pin 2 are ignored,
data on pin XOID (pin 15) are undefined. Transmit data is
clocked off with the positive transition of XCLK. After Reset the
transmit multiframe begin marker is output on pin 68.
11… function of pin 80 XSIG: The signaling information from
the transmit system interface is received on pin XSIG. Bit
FMR5.EIBR should be cleared to disable internal signaling
access from registers XS1...16. The signaling information from
the line interface is transmitted on pin RSIG.
with FALC
QuadFALC
ECLB
CLA4
TM
®
54. Newer FALC devices (e.g. FALC
) don’t support this any more.
199
CLA3
CLA2
CLA1
FALC-LH V1.3
CLA0
E1 Registers
0
PEB 2255
2000-07
(1D)
®
56,