peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 287

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RTO5…RTO0… Receive Time-Slot Offset/Receive Frame Marker Offset
Data Sheet
Release:
Depending on the selected multiframe format the alarm is reset when
FALC-LH does not detect
– the ‘bit 2 = 0’ condition for three consecutive pulse frames
– the ‘FS bit’ condition for three consecutive multiframes (F12),
– the ‘DL pattern’ for three times in a row (ESF).
Depending on bit SIC2.SRFSO this bit enables different functions:
Receive Time-Slot Offset (SIC2.SRFSO = 0)
Initial value which is loaded into the receive time-slot counter at the
trigger edge of SCLKR when the synchronous pulse on port SYPR is
active. Setting of SIC1.SRSC enforces programming the offset values
in a range of 0 to 192 bits.
Receive Frame Marker Offset (SIC2.SRFSO = 1)
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker could be activated during any
bit position of the current frame.
Calculation of the value X of the “Receive Counter Offset” register
RC1/0 depends on the bit position BP which should be marked and
SCLKR:
X = (2BP) mod 386, for SCLKR = 1.544 MHz
(all formats if selected),
287
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07