peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 330

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 3 (Read)
All bits are reset when ISR3 is read.
If bit IPC.VIS is set, interrupt statuses in ISR3 may be flagged although they are masked
via register IMR3. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
ES…
SEC…
XSLP…
LLBSC…
Data Sheet
ISR3
ES
7
Errored Second
This bit is set if at least one enabled interrupt source via ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected
FER = Framing error received
CER = CRC error received
AIS = Alarm indication signal (blue alarm)
LOS = Loss of signal (red alarm)
CVE = Code violation detected
SLIP= Transmit Slip or Receive Slip positive/negative detected
The internal one second timer has expired. The timer is derived from
clock RCLK.
Transmit Slip Indication
Only valid if register SIC1.XBS1/0 = 01.
A one in this bit position indicates that there is an error in the host
clock system. If the wander of the transmit route clock, which normally
is phase locked to a common submultiple of the system clock
(SCLKX), is too great, data transmission errors occur. In that case,
the transmit speech memory has to be reset to its start position by
writing the initial value to the transmit time-slot counter XC1.XTO.
Line Loop Back Status Change/PRBS Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM=0: This bit is set, if the LLB activate signal or the LLB
deactivate signal respective is detected over a period of 33,16 ms
with a bit error rate less than 1/100.
Second Timer
SEC
XSLP
330
LLBSC
RSN
FALC-LH V1.3
T1/J1 Registers
RSP
0
PEB 2255
2000-07
(6B)