peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 30

no-image

peb2255

Manufacturer Part Number
peb2255
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
peb22554H/T
Manufacturer:
INF
Quantity:
5 510
Part Number:
peb22554H/T
Manufacturer:
OMRON
Quantity:
5 510
Part Number:
peb22554HT
Manufacturer:
INFINEON
Quantity:
325
Part Number:
peb22554HT V1.3
Quantity:
1 078
Part Number:
peb22554HT V1.3
Manufacturer:
Infineon
Quantity:
490
Part Number:
peb22554HT2.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
peb22554HTV1.3
Manufacturer:
INFIEON
Quantity:
20 000
Part Number:
peb22554HTV2.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
peb22554V1.3
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
peb2255H
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Table 2
Pin No.
15
Data Sheet
Symbol
XL1
XDOP
XOID
Pin Definitions - Line Interface (cont’d)
Input (I)
Output (O)
Supply (S)
O (analog)
O
O
Line Interface Transmit
Function
Transmit Line 1
Analog output to the external transformer.
Selected if LIM1.DRS = 0. After reset this pin is
in a high impedance state until bit FMR0.XC1 is
set.
Transmit Data Output Positive
This digital output for transmitted dual rail
PCM(+) route signals can provide
- half bauded signals with 50% duty cycle
(LIM0.XFB = 0) or
- full bauded signals with 100% duty cycle
(LIM0.XFB = 1)
The data will be clocked off on the positive
transitions of XCLK in both cases. Output
polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual rail mode is selected
if LIM1.DRS = 1 and FMR0.XC1 = 1. After reset
this pin is in a high impedance state until register
LIM1.DRS is set.
Transmit Optical Interface Data
Unipolar data sent to fiber optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1) which will
be clocked off on the positive transitions of
XCLK. Clocking off data in NRZ code is done
with 100% duty cycle. Data in CMI code (E1
only) are shifted out with 50% or 100% duty
cycle according to the CMI coding. Output
polarity is selected by bit LIM0.XDOS (after
reset: data is sent active high).
The single rail mode is selected if LIM1.DRS = 1
and FMR0.XC1 = 0. After reset this pin is in a
high impedance state until register LIM1.DRS is
set. If LOOP.SPN = 1 this pin function is not
defined and should be tristated by enabling
XPM2.XLT.
30
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07

Related parts for peb2255