peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 210

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Transmit SA4...8 Register (Read/Write)
Value after RESET: 00
XSA8…XSA4… Transmit S
Framer Mode Register 3 (Read/Write)
Value after RESET: 00
XLD…
Data Sheet
FMR3
XSA4
XSA5
XSA6
XSA7
XSA8
XS47
XS57
XS67
XS77
XS87
7
7
The Sa-bit register access is enabled by setting bit FMR1.ENSA = 1.
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XSA4...8 is copied into
a shadow register. The contents is subsequently sent out in the
service words of the next outgoing CRC multiframe (or doubleframes)
if none of the time slot 0 transparent modes is enabled. XS40 is sent
out in bit position 4 in frame 1, XS47 in frame 15. The transmit
multiframe begin interrupt XMB request that these registers should be
serviced. If requests for new information are ignored, current contents
is repeated.
Transmit LLB Down Code
0…
1…
XS46
XS56
XS66
XS76
XS86
H
H
, 00
Normal operation.
A one in this bit position causes the transmitter to replace
normal transmit data with the LLB Down (Deactivate) Code
continuously until this bit is reset. The LLB Down Code is
optionally overwritten by the timeslot 0 depending on bit
H
XS45
XS55
XS65
XS75
XS85
XLD
, 00
a
-Bit Data
H
, 00
XS44
XS54
XS64
XS74
XS84
XLU
H
, 00
210
H
XS43
XS53
XS63
XS73
XS83
CMI
SA6SY
XS42
XS52
XS62
XS72
XS82
CFRZ
XS41
XS51
XS61
XS71
XS81
FALC-LH V1.3
EXTIW
XS40
XS50
XS60
XS70
XS80
E1 Registers
0
0
PEB 2255
2000-07
(2C)
(2D)
(2A)
(2B)
(2E)
(2F)