peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 272

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Mask Register 0...5
Value after RESET: FF
IMR0...5...
Framer Mode Register 0 (Read/Write)
Value after RESET: 00
XC1…0…
Data Sheet
FMR0
IMR0
IMR1
IMR2
IMR3
IMR4
IMR5
CASE
RME
FAR
XSP
XC1
LFA
ES
7
7
Interrupt Mask Register
Each interrupt source can generate an interrupt signal on port INT
(characteristics of the output stage are defined via register IPC). A ‘1’
in a bit position of IMR0…5 sets the mask active for the interrupt
status in ISR0…3 and ISR5. Masked interrupt statuses neither
generate a signal on INT, nor are they visible in register GIS.
Moreover, they are
– not displayed in the Interrupt Status Register if bit IPC.VIS is
– displayed in the Interrupt Status Register if bit IPC.VIS is set.
After RESET, all interrupts are disabled.
Transmit Code
Serial code transmitter is independent to the receiver.
00… NRZ (optical interface)
01… Not assigned
RDO
SEC
XSN
RFS
FER
XC0
LFA
cleared
H
H
, FF
MFAR
XSLP
ALLS
H
CER
RC1
ISF
, FF
H
, FF
LMFA
RMB
XDU
RC0
AIS
H
,FF
272
H
LLBSC
RSC
XMB
LOS
FRS
AIS
CRC6
SRAF
LOS
CVE
PDEN
XLSC
EXLS
SLIP
RAR
RSN
FALC-LH V1.3
T1/J1 Registers
XPR
RSP
RPF
SIM
RA
0
0
PEB 2255
2000-07
(1A)
(14)
(15)
(16)
(17)
(18)
(19)