peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 231

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RES4…0...
Framer Receive Status Register 0 (Read)
LOS…
Data Sheet
FRS0
LOS
7
The current line attenuation status in steps of about 1.7 dB are
displayed in these bits. Only valid if bits EV1...0 = 01 and
LIM1.EQON=1. Accuracy: +/- 2 digit, based on temperature influence
and noise amplitude variations.
00000… attenuation (0 dB)
...
11001… max. attenuation
Detection:
This bit is set when the incoming signal has “no transitions” (analog
interface) or logical zeros (digital interface) in a time interval of T
consecutive pulses, where T is programmable by register PCD.
Total account of consecutive pulses: 16 < T < 4096.
Analog interface: The receive signal level where “no transition” is
declared is defined by the programmed value of LIM1.RIL2...0 (short
haul mode only, LIM1.EQON = 0).
Recovery:
Analog interface: The bit is reset in short haul mode when the
incoming signal has transitions with signal levels greater than the
programmed receive input level (LIM1.RIL2...0; short haul mode only)
for at least M pulse periods defined by register PCR in the PCD time
interval.
Digital interface: The bit is reset when the incoming data stream
contains at least M ones defined by register PCR in the PCD time
interval.
With the rising edge of this bit an interrupt status bit (ISR2.LOS) is set.
For additional recovery conditions see register LIM2.LOS2...1.
The bit is also set during alarm simulation and reset if FMR0.SIM is
cleared and no alarm condition exists.
Receive Equalizer Status
Loss of Signal
AIS
LFA
RRA
231
AUXP
NMF
LMFA
FALC-LH V1.3
E1 Registers
0
PEB 2255
2000-07
(4C)